View LTC2926CUFD_4342248.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC2926 MOSFET-Controlled Power Supply Tracker FEATURES

DESCRIPTIO
Flexible Power Supply Tracking and Sequencing Adjustable Ramp Rates, Offsets and Time Delays Controls Three Supplies with Series MOSFETs Integrated Remote Sense Switching FAULT Input/Output STATUS Output/Power Good Input Available in 20-Lead Narrow SSOP and 20-Lead QFN (4mm x 5mm) Packages
The LTC2926 provides a simple solution for tracking and sequencing up to three power supply rails. An N-channel MOSFET and a few resistors per channel configure the load voltages to ramp up and down together, with voltage offsets, with time delays or with different ramp rates. Automatic remote sense switching compensates for voltage drops across the MOSFETs. The LTC2926 provides two integrated switches as well as a signal to control optional additional external N-channel MOSFET sense switches. The LTC2926 includes I/O signals for communication with other devices. The status output asserts after tracking and sequencing have completed. A low voltage on the power good input after an adjustable timeout period causes load disconnect. A low voltage on the fault I/O causes immediate load disconnect. Until it is reset, a fault latch prevents tracking and keeps the loads disconnected.
APPLICATIO S

VCORE and VI/O Supply Tracking Microprocessor, DSP and FPGA Supplies Servers Communications Systems
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents including 6897717.
TYPICAL APPLICATIO
1.8V MODULE OUT 100 SENSE
IRF7413Z
1.8V SLAVE1
10
500mV/DIV
3.3V MODULE OUT 100 SENSE VCC 0.1F 10 SGATE2 SGATE1 S1 15.0k D2 RAMPBUF 15.0k 15.0k 9.53k TRACK2 4.02k 10k FAULT ON/OFF FAULT ON GND PGTMR VCC STATUS/PGI MGATE RAMP
2926 TA01
IRF7413Z
3.3V SLAVE2
D1
FB1 9.53k S2
3.3V SLAVE2
TRACK1 LTC2926 FB2 VCC 10k
15.0k
1.8V SLAVE1 500mV/DIV
4.02k
STATUS
0.1F
1F
U
3.3V SLAVE2 1.8V SLAVE1 5ms/DIV
2926 TA01b
U
U
5ms/DIV
2926 TA01c
2926fa
1
LTC2926 ABSOLUTE
(Notes 1, 2)
AXI U RATI GS
RMS Currents TRACK1, TRACK2 ................................................5mA FB1, FB2 ..............................................................5mA D1, S1, D2, S2 ...................................................30mA Operating Temperature LTC2926C ................................................ 0C to 70C LTC2926I ............................................. -40C to 85C Storage Temperature Range GN Package ....................................... -65C to 150C UFD Package...................................... -65C to 125C Lead Temperature (Soldering, 10 sec) GN Package ...................................................... 300C
Supply Voltage (VCC) ................................. -0.3V to 10V Input Voltages ON ......................................................... -0.3V to 10V RAMP .............................................-0.3V to VCC + 1V TRACK1, TRACK2 ........................-0.3V to VCC + 0.3V PGTMR ........................................-0.3V to VCC + 0.3V Input/Output Voltages FAULT .................................................... -0.3V to 10V STATUS/PGI (Note 3) .......................... -0.3V to 11.5V Output Voltages RAMPBUF ....................................-0.3V to VCC + 0.3V FB1, FB2, D1, S1, D2, S2 ....................... -0.3V to 10V MGATE, RSGATE (Note 3)................... -0.3V to 11.5V SGATE1, SGATE2 (Note 3) .................. -0.3V to 11.5V
PACKAGE/ORDER I FOR ATIO
TOP VIEW VCC TRACK1 FB1 S1 SGATE1 D1 ON PGTMR FAULT 1 2 3 4 5 6 7 8 9 20 RAMPBUF 19 TRACK2 18 FB2 17 S2 16 SGATE2 15 D2 14 STATUS/PGI 13 RSGATE
RAMPBUF
TRACK1
20 19 18 17 FB1 1 S1 2 SGATE1 3 D1 4 ON 5 PGTMR 6 7 FAULT 8 GND 9 10 RAMP MGATE 21 16 FB2 15 S2 14 SGATE2 13 D2 12 STATUS/PGI 11 RSGATE
12 MGATE 11 RAMP
GND 10
GN PACKAGE 20-LEAD PLASTIC SSOP TJMAX = 125C, JA = 85C/W
UFD PACKAGE 20-LEAD (4mm x 5mm) PLASTIC QFN EXPOSED PAD (PIN 21) IS GND PCB CONNECTION OPTIONAL TJMAX = 125C, JA = 43C/W
ORDER PART NUMBER LTC2926CGN LTC2926IGN
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/
ORDER PART NUMBER LTC2926CUFD LTC2926IUFD
UFD PART MARKING* 2926 2926
Consult LTC Marketing for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.
TRACK2
VCC
2
U
U
W
WW U
W
TOP VIEW
2926fa
LTC2926 ELECTRICAL CHARACTERISTICS
SYMBOL Supply Voltage VCC ICC Input Supply Voltage Input Supply Current Operating Range ITRACKn = 0mA, IFBn = 0mA, IRAMPBUF = 0mA ITRACKn = -1mA, IFBn = -1mA, IRAMPBUF = -3mA VCC(UVLO) VCC(UVLO) Control and I/O VON(TH) VON(TH) ION VON(CLR) tCLR VON(ARM) tARM VFAULT(TH) IFAULT(UP) VFAULT(OL) VFAULT(OH) VPGI(TH) VPGI(TH) IPGI(UP) VSTATUS(OL) VSTATUS(OH) VPGTMR(TH) IPGTMR(UP) IPGTMR(DN) VPGTMR(CLR) Ramp Buffer IRAMP(IN) VRAMPBUF(OS) VRAMPBUF(OL) RAMP Pin Input Current Ramp Buffer Offset Voltage RAMPBUF Pin Output Low Voltage 0V < VRAMP < 5.5V, VCC = 5.5V VRAMP = 1/2 VCC, IRAMPBUF = 0mA IRAMPBUF = 3mA

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V unless otherwise specified.
PARAMETER CONDITIONS MIN 2.9 1.5 8.5 2.2 15 TYP 3.3 2.5 9.5 2.4 50 MAX 5.5 3.5 10.5 2.6 75 UNITS V mA mA V mV
Input Supply Undervoltage Lockout Input Supply Undervoltage Lockout Hysteresis ON Pin Threshold Voltage ON Pin Threshold Voltage Hysteresis ON Pin Input Current ON Pin Fault Clear Threshold Voltage Fault Clear Delay ON Pin Fault Arm Threshold Voltage Fault Arm Delay FAULT Pin Input Threshold Voltage FAULT Pin Pull-up Current FAULT Pin Output Low Voltage FAULT Pin Output High Voltage (VCC - VFAULT) STATUS/PGI Pin Input Threshold Voltage STATUS/PGI Pin Input Threshold Voltage Hysteresis STATUS/PGI Pin Pull-Up Current STATUS/PGI Pin Output Low Voltage STATUS/PGI Pin Output High Voltage (VSTATUS/PGI - VCC) PGTMR Pin Threshold Voltage PGTMR Pin Pull-Up Current PGTMR Pin Pull-Down Current PGTMR Pin Clear Threshold Voltage
VCC Rising
VON Rising VON = 1.2V, VCC = 5.5V VON Falling VON Falling VON Rising VON Rising VFAULT Falling Fault Latch Clear, VFAULT = 1.5V Fault Latch Set, IFAULT = 5mA, VCC = 2.7V Fault Latch Clear, IFAULT = -1A VSTATUS/PGI Rising

1.20 40 0.465 1 0.565 1 0.465 -3.0 300 1.10 30 -7 5.0 1.10 -8 0.5 50
1.23 75 0 0.500 3 0.600 4.5 0.500 -8.5 100 550 1.23 75 -10 200 5.5 1.23 -10 4 100 0 0 32
1.26 110 100 0.535 10 0.635 10 0.535 -13 400 900 1.36 150 -13 400 6.0 1.36 -12 10 150 1 10 60
V mV nA V s V s V A mV mV V mV A mV V V A mA mV A mV mV
STATUS/PGI On, VSTATUS/PGI = 1.5V VON Low, ISTATUS/PGI = 5mA, VCC = 2.7V ISTATUS/PGI = -1A VPGTMR Rising ON High, VPGTMR = 1V ON Low, VPGTMR = 0.1V, VCC = 2.7V VPGTMR Falling

2926fa
3
LTC2926
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V unless otherwise specified.
SYMBOL VRAMPBUF(OH) Tracking Channels IERROR(%) VTRACK VFB(REF) IFB(LEAK) VFB(CLAMP) VMGATE IMGATE(UP) IMGATE(DN) IMGATE(FAULT) Slave Supplies VSGATE ISGATE(UP) ISGATE(DN) ISGATE(UPFST) ISGATE(DNFST) ISGATE(FAULT) SGATE Pins External N-Channel Gate Drive (VSGATEn - VCC) SGATE Pins Pull-Up Current SGATE Pins Pull-Down Current SGATE Pins Fast Pull-Up Current SGATE Pins Fast Pull-Down Current SGATE Pins Fault Pull-Down Current ISGATEn = -1A, VFBn = 0.75V Fault Latch Clear, VFBn = VFB(REF) - 10mV, VSGATEn = 3.3V Fault Latch Clear, VFBn = VFB(REF) + 10mV, VSGATEn = 3.3V Fault Latch Clear, VFBn = 0V, VSGATEn = 3.3V Fault Latch Clear, VFBn = 1V, VSGATEn = 3.3V Fault Latch Set, VON High, VSGATEn = 5.5V, VCC = 5.5V IRSGATE = -1A Fault Latch Clear, Switches On, VRSGATE = 0V Fault Latch Clear, Switches Off, VRSGATE = 3.3V Fault Latch Set, Switches Off, VRSGATE = 5.5V, VCC = 5.5V Ramping Completed on Pin Low, RSGATE Falling Switches On, VDn = VCC + 0.3V, ISn = -10mA

ELECTRICAL CHARACTERISTICS
PARAMETER RAMPBUF Pin Output High Voltage (VCC - VRAMPBUF) IFBn to ITRACKn Current Mismatch (IFBn - ITRACKn)/ITRACKn * 100% TRACK Pins Voltage FB Pins Internal Reference Voltage FB Pins Leakage Current FB Pins Clamp Voltage MGATE Pin External N-Channel Gate Drive (VMGATE - VCC) MGATE Pin Pull-Up Current MGATE Pin Pull-Down Current MGATE Pin Fault Pull-Down Current
CONDITIONS IRAMPBUF = -3mA
MIN
TYP 60
MAX 80
UNITS mV
ITRACKn = -10A ITRACKn = -1mA ITRACKn = -10A ITRACKn = -1mA VTRACKn = VCC, IFBn = 0mA VFBn = 0.8V, VCC = 5.5V -1mA < IFBn < -1A IMGATE = -1A Fault Latch Clear, VON High, VMGATE = 3.3V Fault Latch Clear, VON Low, VMGATE = 3.3V Fault Latch Set, VON High, VMGATE = 5.5V, VCC = 5.5V

0 0 0.776 0.776 0.784 1.7 5.0 -7 7 5 0.800 0.800 0.800 0 2.0 5.5 -10 10 20
3 3 0.824 0.824 0.816 10 2.4 6.0 -13 13 50
% % V V V nA V V A A mA
Master Ramp and Supply
5.0 -6 6 -21 21 5
5.5 -10 10 -30 30 20
6.0 -13 13 -39 39 50
V A A A A mA
Remote Sense Switches VRSGATE IRSGATE(UP) IRSGATE(DN) IRSGATE(FAULT) VRSGATE(TH) RSW(ON) RSGATE Pin External N-Channel Gate Drive (VRSGATE - VCC) RSGATE Pin Pull-Up Current RSGATE Pin Pull-Down Current RSGATE Pin Fault Pull-Down Current RSGATE Pin Threshold Voltage Remote Sense Switch On-Resistance

5.0 -7 7 5 1.10
5.5 -10 10 20 1.23 2
6.0 -13 13 50 1.36 10
V A A mA V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 3: The MGATE, SGATE1, SGATE2, RSGATE and STATUS/PGI pins are internally limited to a minimum of 11.5V. Driving these pins to voltages beyond the clamp level may damage the part.
2926fa
4
LTC2926 TYPICAL PERFOR A CE CHARACTERISTICS
unless otherwise specified. Supply Current vs Supply Voltage
12 10 8 ICC (mA) 6 4 2 0 2.5 IRAMPBUF = 0mA ITRACKn = 0mA IFBn = 0mA IRAMPBUF = -3mA ITRACKn = -1mA IFBn = -1mA 12 10 8 ICC (mA) 6 4 2 0 -50 IRAMPBUF = 0mA ITRACKn = 0mA IFBn = 0mA IRAMPBUF = -3mA ITRACKn = -1mA IFBn = -1mA
VTRACK (V)
3.0
3.5
4.0 4.5 VCC (V)
5.0
Gate Drive Voltages vs Supply Voltage
6.0 MGATE, RSGATE, SGATE1, SGATE2 PINS 6 5 GATE DRIVE (V) 4 3 2 1 0 3.0 3.5 4.0 4.5 VCC (V) 5.0 5.5 6.0
5.8 GATE DRIVE (V)
5.6
IGATE(PD) (mA)
5.4
5.2
GATE DRIVE = VPIN - VCC IGATE = -1A
5.0 2.5
MGATE, RSGATE Fault Pull-Down Currents vs Temperature
30 25 ISGATE(PD) (mA) 20 15 10 5 0 -50 FAULT LATCH SET VCC = 3.3V VCC = 5.5V MGATE, RSGATE PINS 30 25 20 15 10 5
IMGATE(PD), IRSGATE(PD) (mA)
-25
UW
5.5
Specifications are at TA = 25C, VCC = 3.3V
Supply Current vs Temperature
0.812 0.808 0.804 0.800 0.796 0.792
Track Pin Voltage vs Temperature
ITRACK = -10A
ITRACK = -1mA
6.0
-25
0 25 50 TEMPERATURE (C)
75
100
2926 G02
0.788 -50
-25
0 25 50 TEMPERATURE (C)
75
100
2926 G03
2926 G01
Gate Drive Voltages vs Load Current
GATE DRIVE = VPIN - VCC SGATE1, SGATE2 PINS FAST PULL-UP MODE 30 25 20 15 10 5
Gate Fault Pull-Down Currents vs Supply Voltage
MGATE, RSGATE, SGATE1, SGATE2 PINS
MGATE, RSGATE, SGATE1, SGATE2 PINS PULL-UP MODE
FAULT LATCH SET
0
5
10
15 20 ILOAD (A)
25
30
35
0 2.5
3.0
3.5
4.0 4.5 VCC (V)
5.0
5.5
6.0
2926 G05
2926 G06
2926 G07
SGATE Fault Pull-Down Current vs Temperature
SGATE1, SGATE2 PINS
VCC = 5.5V
VCC = 3.3V
VCC = 2.9V
FAULT LATCH SET
VCC = 2.9V
0 25 50 TEMPERATURE (C)
75
100
2926 G08
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
2926 G09
2926fa
5
LTC2926 TYPICAL PERFOR A CE CHARACTERISTICS
unless otherwise specified. RAMPBUF Output Low Voltage vs Temperature
50 IRAMPBUF = 3mA 100
40
VCC = 2.9V VOH (mV)
VOL (mV)
20
VCC = 5.5V
40
VCC = 5.5V
VOL (mV)
30
10
0 -50
-25
0 25 50 TEMPERATURE (C)
6
UW
75
Specifications are at TA = 25C, VCC = 3.3V Logic Output Low Voltages vs Supply Voltage
250 STATUS/PGI PIN 200 ISTATUS/PGI = 5mA 150
RAMPBUF Output High Voltage vs Temperature
IRAMPBUF = -3mA VOH = VCC - VRAMPBUF VCC = 2.9V 60
80
100
FAULT PIN IFAULT = 5mA
20
50
100
2926 G10
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
2926 G11
0 2.5
3.0
3.5
4.0 4.5 VCC (V)
5.0
5.5
6.0
2926 G12
2926fa
LTC2926 PI FU CTIO S GN/UFD Packages
D1, S1, D2, S2 (Pins 6, 4, 15, 17/Pins 4, 2, 13, 15): Remote Sense Switches #1 and #2. A 10 (max) switch connects each pair of pins (D1/S1 and D2/S2) after MGATE, SGATE1 and SGATE2 are all fully enhanced (MGATE > RAMP + 4.9V or RAMP > VCC, and SGATE1, SGATE2 > VCC + 4.9V). The switch can be used to compensate for the voltage drop across the external MOSFET that controls a slave or the master supply. Connect the switch between the load and the supply's sense node. Before the external MOSFET is fully enhanced, a resistor between the supply's output and sense nodes provides local feedback. When the ON pin voltage is low, the switch will open before the MGATE, SGATE1 and SGATE2 pins will ramp down. Leave unused switch terminal pairs unconnected. Exposed Pad (Pin 21, UFD Package Only): Exposed pad may be left open or connected to device GND. FAULT (Pin 9/Pin 7): Negative-Logic Fault Input/Output. Under normal conditions the internal fault latch is not set and an 8.5A current pulls up FAULT to a diode drop below VCC. When the voltage at FAULT is pulled below 0.5V, a fault condition is latched and an internal N-channel MOSFET pulls FAULT to GND until the latch is reset. The fault condition also pulls STATUS/PGI low, opens the remote sense switches, and pulls MGATE, SGATE1 and SGATE2 to GND to disconnect the master and slave supplies from their loads. Pulling STATUS/PGI below 1V after the power good time-out delay also latches a fault. The fault latch is reset when the ON pin voltage is below 0.5V, or when VCC is undervoltage. The fault latch is armed when the ON pin voltage exceeds 0.6V. To auto-retry after a fault, connect FAULT to the ON pin. Leave the FAULT pin unconnected if it is unused. FB1, FB2 (Pins 3, 18/Pins 1, 16): Feedback Control Input/Outputs. Each FB pin connects to the feedback node of a slave supply. Connect an FB pin to the tap point of a resistive voltage divider between the source (load side) of the external MOSFET and GND. For a slave supply with an accessible feedback path, no external MOSFET may be necessary. In that case, connect an FB pin to the tap point of a resistive voltage divider between the supply generator's feedback node and GND. To prevent damage to the slave supply, the FB pins will not force the slave's feedback node above 2.4V. In addition, it will not actively sink current even when the LTC2926 is not powered. Tie unused FB pins to GND. GND (Pin 10/Pin 8): Device Ground. MGATE (Pin 12/Pin 10): Master Gate Drive for External N-Channel MOSFET/Master Ramp. When the ON pin is high, an internal 10A current charges the gate of an external N-channel MOSFET. A capacitor from MGATE to GND sets the master ramp rate. Add a 10 resistor between the capacitor and the MOSFET's gate to prevent high frequency oscillations. An internal charge pump guarantees that the MGATE pin voltage will pull up to 5.5V above VCC, which ensures that logic-level N-channel MOSFETs are fully enhanced. When the ON pin is pulled low, the MGATE pin is pulled to GND by a 10A current source. Upon a fault condition, the MGATE pin is pulled low immediately with 20mA. To create a master ramp signal without an external MOSFET, tie the MGATE pin to the RAMP pin. A weak internal clamp on the RAMP pin limits MGATE to VCC + 1V in this case. Leave the MGATE pin unconnected if it is unused. ON (Pin 7/Pin 5): On Control Input. The ON pin has a threshold of 1.23V with 75mV of hysteresis. A high causes 10A to flow out of the MGATE pin, ramping up the supplies. A low causes 10A to flow into the MGATE pin, ramping down the supplies. Pull the ON pin below 0.5V to reset the fault latch. Pull the ON pin above 0.6V after a fault latch reset to arm the fault latch. PGTMR (Pin 8/Pin 6): Power Good Timer. Connect an external capacitor between PGTMR and GND to set the Power Good Time-Out Delay. When the ON pin is above 1.23V, a 10A current pulls up PGTMR to VCC, otherwise an internal N-channel MOSFET pulls PGTMR to GND. If the voltage on PGTMR exceeds 1.23V and the voltage on STATUS/PGI is not above 1.23V, a fault condition is latched, the remote sense switches are opened, and FAULT, STATUS/PGI, MGATE, SGATE1, SGATE2 and RSGATE will be immediately pulled to GND. To disable the Power Good Timer tie PGTMR to GND.
U
U
U
2926fa
7
LTC2926 PI FU CTIO S GN/UFD Packages
RAMP (Pin 11/ Pin 9): Ramp Buffer Input. Connect the RAMP pin to the master ramp signal to force the slave supplies to track it. When the RAMP pin is connected to the source of an external N-channel MOSFET, the slave supplies track the MOSFET's source, the master supply voltage, as it ramps up and down. When a master supply is not required, the RAMP pin can be tied directly to the MGATE pin to form a master ramp voltage. In this configuration, the supplies track the capacitor on the MGATE pin as it is charged and discharged by the 10A current source that is controlled by the ON pin. The RAMP pin is weakly clamped to VCC + 1V. Do not drive RAMP above VCC with a low impedance source to avoid sinking large currents into the pin. Ground the RAMP pin if it is unused. RAMPBUF (Pin 20/Pin 18): Ramp Buffer Output. The RAMPBUF pin provides a low impedance buffered version of the signal on the RAMP pin. This buffered output drives the resistive voltage dividers that connect to the TRACK pins. Limit the capacitance at the RAMPBUF pin to less than 100pF. RSGATE (Pin 13/Pin 11): Gate Drive for Internal and External N-Channel MOSFET Remote Sense Switches. A remote sense path between a load and the sense input of its supply generator automatically compensates for voltage drops across the tracking MOSFET. After the series MOSFETs are fully enhanced, a 10A current pulls up RSGATE. An internal charge pump guarantees that RSGATE will pull up to 5.5V above VCC, which ensures that logic-level N-channel MOSFETs are fully enhanced. When the voltage at RSGATE exceeds VCC + 4.9V, the STATUS/PGI pull-down is released. When the ON pin is low, a 10A current source pulls RSGATE to GND. Supplies will not track down until the RSGATE pin voltage falls below 1.23V, which ensures that the remote sense switches open before the loads are disconnected. Connect RSGATE to the gates of additional external N-channel MOSFETs to create more remote sense switches. Upon a fault condition, the RSGATE pin is pulled low immediately with 20mA. Optionally connect a capacitor between RSGATE and GND to set the switch-on rate or to add delay between switch closure and STATUS/PGI assertion. Leave RSGATE unconnected if it is unused. SGATE1, SGATE2 (Pins 5, 16/Pins 3, 14): Slave Gate Controllers for External N-Channel MOSFETs. Each SGATE pin ramps a slave supply by controlling the gate of an external N-channel MOSFET so that its source terminal follows the tracking profile set by external resistors and the master ramp. It is a good practice to add a 10 resistor between this pin and the MOSFET's gate to prevent high frequency oscillations. An internal charge pump guarantees that the SGATE pin voltage will pull up to 5.5V above VCC, which ensures that logic-level N-channel MOSFETs are fully enhanced. Leave unused SGATE pins unconnected. STATUS/PGI (Pin 14/Pin 12): Status Output/Power Good Input. A 10A current pulls up STATUS/PGI when MGATE, SGATE1 and SGATE2 are fully enhanced, and the remote sense switches are closed, otherwise an internal N-channel MOSFET pulls down STATUS/PGI. If the STATUS/PGI pin is pulled below 1V after the power-good time-out delay (see PGTMR pin description), the fault latch is set, and MGATE, SGATE1, SGATE2 and RSGATE are all pulled low immediately. An internal charge pump guarantees that the STATUS/PGI pin voltage will pull up to 5.5V above VCC. An external pull-up resistor may be added to limit the STATUS/PGI voltage to logic levels. Leave the STATUS/PGI pin unconnected if it is unused. TRACK1, TRACK2 (Pins 2, 19/Pins 20, 17): Tracking Control Inputs. A resistive voltage divider between RAMPBUF and each TRACK pin determines the tracking profile of each supply channel. Each TRACK pin pulls up to 0.8V, and the current supplied at TRACK is mirrored at FB. The TRACK pins are capable of supplying at least 1mA when VCC = 2.9V. They may be capable of supplying up to 10mA when the supply is at 5.5V, so care should be taken not to short this pin for extended periods. Limit the capacitance at the TRACK pins to less than 25pF. Leave unused TRACK pins unconnected. VCC (Pin 1/Pin 19): Positive Voltage Supply. Operating range is from 2.9V to 5.5V. An undervoltage lockout resets the part when the supply is below 2.4V. VCC should be bypassed to GND with a 0.1F capacitor.
8
U
U
U
2926fa
LTC2926 FU CTIO AL BLOCK DIAGRA
2.4V VCC ON 0.6V 0.5V + - CLEAR/ARM SIGNAL LATCH + - + - + 1.23V - VCC 10A + - 0.1V PGTMR + - 0.5V DELAY DELAY R S Q CLR/ARM FAULT LATCH R S Q FAULT FAULT 8.5A UVLO
RSGATE VCC + 4.9V RSGATE 1.23V MGATE RAMP + 4.9V RAMP VCC SGATE1 VCC + 4.9V SGATE2 VCC + 4.9V D1 D2
+ - + - + - + - + -
+ - S1 S2 VCC 0.8V + - 10A/30A FAST PULL-DOWN FB2 FB1 1x GND
2926 BD
TRACK2 TRACK1 RAMPBUF
0.8V
+ -
W
VCC FAST PULL-DOWN VCC UVLO + - PGI LOW + - UVLO CHARGE PUMP 10A GATE UP FAST PULL-DOWN MGATE 1.23V 1.23V 10A STATUS/PGI CHARGE PUMP PGTMR HIGH 10A CHARGE PUMP 10A RSGATE UP FAST PULL-DOWN RSGATE 10A CHARGE PUMP 10A/30A VCC UP/DOWN SGATE1 SGATE2 RAMP
2926fa
U
U
9
LTC2926 APPLICATIO S I FOR ATIO
Power Supply Tracking and Sequencing The LTC2926 handles a variety of power-up profiles to satisfy the requirements of digital logic circuits including FPGAs, PLDs, DSPs and microprocessors. These requirements fall into one of the four general categories illustrated in Figures 1 to 4. Some applications require that the potential difference between two power supplies must never exceed a specified voltage. This requirement applies during power-up and power-down as well as during steady-state operation, often to prevent destructive latch-up in a dual supply IC. Typically, this is achieved by ramping the supplies up and down together (Figure 1). In other applications it is desirable to have the supplies ramp up and down ratiometrically (Figure 2) or with fixed voltage offsets between them (Figure 3). Certain applications require one supply to come up after another. For example, a system clock may need to start before a block of logic. In this case, the supplies are sequenced as in Figure 4, where the 1.8V supply ramps up completely followed by the 2.5V supply.
MASTER SLAVE2 SLAVE1 500mV/DIV 500mV/DIV SLAVE2 SLAVE1
5ms/DIV
2926 F01
Figure 1. Coincident Tracking
MASTER SLAVE2 SLAVE1 500mV/DIV 500mV/DIV
5ms/DIV
2926 F03
Figure 3. Offset Tracking
10
U
Operation The LTC2926 provides a simple solution to allow all of the power supply tracking and sequencing profiles shown in Figures 1 to 4. A single LTC2926 controls up to three supplies: two "slave" supplies that track a "master" signal. With just four resistors and an external N-channel MOSFET, each slave supply is configured to ramp up and down as a function of the master signal. This master signal can be a third supply that is ramped up through an external MOSFET, whose ramp rate is set with a single capacitor, or it can be a signal generated by tying the MGATE and RAMP pins together to an external capacitor. Tracking Cell and Gate Controller Cell The LTC2926's operation is based on the combination of a tracking cell and a gate controller cell that is shown in Figure 5. The tracking cell servos the TRACK pin at 0.8V, and the current supplied by the TRACK pin is mirrored at the FB pin. The gate controller cell servos the FB pin at 0.8V by driving the gate of the external N-channel MOSFET (QEXT), and establishes the slave output voltage at the source of the MOSFET based on the TRACK pin current and resistors
5ms/DIV
2926 F02
W
U
U
Figure 2. Ratiometric Tracking
SLAVE2 SLAVE1
5ms/DIV
2926 F04
Figure 4. Supply Sequencing
2926fa
LTC2926 APPLICATIO S I FOR ATIO
SUPPLY LTC2926 VCC 0.8V TRACKING CELL GATE CONTROLLER CELL VCC + 5V
+
MASTER RAMP RTB
-
TRACK ITRACK IFB
RTA
Figure 5. Simplified Tracking Cell and Gate Controller Cell Combination
RFA and RFB. The slave output voltage varies as a function of the master signal with terms set by RTA and RTB. By selecting appropriate values of RTA and RTB, it is possible to generate any of the profiles in Figures 1 to 4. Controlling the Ramp-Up and Ramp-Down Behavior The operation of the LTC2926 is most easily understood by referring to the simplified functional diagram in Figure 6. When the ON pin is low, the remote sense switch is opened and the MGATE pin is pulled to ground causing the master signal to remain low. Since the current through RTB1 is at its maximum when the master signal is low, the current sourced by FB1 is also at its maximum. The current forces the FB1 pin voltage above 0.8V, which pulls the SGATE1 pin low and disconnects the slave's supply generator. The minimum voltage across the slave load is a function of the maximum FB1 current, the feedback divider resistors, and the load resistance (see Load Requirements). When the ON pin rises above 1.23V, the master signal ramps up, and the slave supply tracks the master signal. The master ramp rate is set by an external capacitor driven by a 10A current source from an internal charge pump. If no external MOSFET is used for the master signal, the ramp rate is set by tying the MGATE and RAMP pins together at one terminal of the external capacitor (see Ratiometric Tracking Example or Supply Sequencing Example). The MGATE pin voltage will be limited to VCC + 1V (max) by the weak internal clamp on the RAMP pin.
U
QEXT SLAVE
W
U
U
+ -
10A SGATE
0.8V 10A
RFB FB RFA
2926 F05
The rising master signal decreases the tracking current mirrored out of the FB1 pin. The gate controller circuitry maintains 0.8V at FB1 by driving the SGATE1 voltage and, via the external MOSFET source-follower, the slave supply output. When the slave supply output reaches the slave supply module voltage, the FB1 pin will fall below 0.8V and the gate controller will drive the SGATE1 pin above VCC to fully enhance the MOSFET. After the MGATE, SGATE1 and SGATE2 pins reach their maximum voltages, the RSGATE pin is pulled up by a 10A current source from an internal charge pump, which closes the integrated remote sense switches. The integrated remote sense switch allows the slave supply generator to compensate for voltage drop across the slave's MOSFET (Q1). When the ON pin falls below VON(TH) - VON(TH), typically 1.16V, the remote sense switch opens and the MGATE pin pulls down with 10A. The master signal and the slave supplies will fall at the same rate as they rose previously, following the tracking or sequencing profile in reverse. The ON pin can be controlled by a digital I/O pin or it can be used to monitor an input supply. By connecting a resistive voltage divider from an input supply to the ON pin, the supplies will ramp up only after the monitored supply reaches a preset voltage.
2926fa
11
LTC2926 APPLICATIO S I FOR ATIO
SUPPLY MODULE Q0 OUT MASTER
SUPPLY MODULE Q1 OUT RX1 SENSE VCC MGATE RAMP SLAVE1
D1
MGATE
+ -
CHARGE PUMP
RAMP + 4.9V
SGATE1
+ -
VCC + 4.9V
SGATE2
+ -
CHARGE PUMP 10A
VCC + 4.9V
ON/OFF
ON
+
1.23V
-
10A 1x VCC CHARGE PUMP 0.8V
RAMPBUF
0.8V
+ - -
10A
RTB1
TRACK1 GND
RTA1
Figure 6. Simplified Functional Block Diagram
Optional Master Supply MOSFET Figure 7 illustrates how an optional external N-channel MOSFET (device Q0) can ramp up a supply that doubles as the master signal. The MOSFET's gate is tied to the MGATE pin and its source is tied to the RAMP pin. The MGATE pin sources or sinks 10A to ramp the MOSFET's gate up or down at a rate set by the external capacitor connected to
12
U
CMGATE REMOTE SENSE SWITCH S1 10A TO RSGATE PIN 10A
W
U
U
+
10A SGATE1
RFB1 FB1 RFA1
2926 F06
the MGATE pin. The series MOSFET controls any supply with an output voltage between 0V and VCC. To compensate for voltage drop across the master supply MOSFET, add an optional external remote sense switch (device Q3 in Figure 7) connected between RAMP and the sense input of the master voltage supply module. Tie the gate of the external switch MOSFET to the RSGATE pin for automatic remote sense switching.
2926fa
LTC2926 APPLICATIO S I FOR ATIO
3.3V MODULE Q0 VIN IN OUT RX0 SENSE 10 1.8V MODULE Q1 VIN IN OUT RX1 SENSE 10 SENSE 1.8V SLAVE1 VIN 2.5V MODULE Q2 IN OUT RX2 NC CMGATE 10 2.5V SLAVE2 Q3 SENSE MASTER VIN IN OUT RX1 10
2.5V MODULE Q2 VIN IN OUT RX2 SENSE RSGATE D1 D2 VIN 0.1F RTB1 TRACK1 RTA1 RTB2 TRACK2 RTA2 10k FAULT ON/OFF FAULT ON GND PGTMR STATUS/PGI
2926 F07
CMGATE 10 MGATE RAMP SGATE1 SGATE2
VCC RAMPBUF
S1 S2 RFB1 LTC2926 FB1 RFA1 RFB2 FAULT ON/OFF RTA2 10k VIN
VIN
FB2 VIN 10k STATUS RFA2
CPGTMR
Figure 7. Typical Application with Master Supply
Ramp Buffer The RAMPBUF pin provides a buffered version of the RAMP pin voltage that drives the resistive dividers on the TRACK pins. When there is no external MOSFET, it sources or sinks up to 3mA to drive the track resistors even though the MGATE pin only supplies 10A (Figure 8). The RAMPBUF pin also proves useful in systems with an external MOSFET. If RTBn were directly connected to the MOSFET's source (the master output), the servo mechanism of the tracking cell could potentially drive the master output towards 0.8V when the MOSFET is off. The ramp buffer prevents this by eliminating that path for current. Fault Input/Output The FAULT pin allows external upstream monitoring circuits to control and to communicate with the LTC2926. The pin is driven internally by an N-channel MOSFET pull-down to GND, and by an 8.5A pull-up to VCC through a series diode. Under normal conditions, the MOSFET is off and the
U
1.8V MODULE Q1 1.8V SLAVE1 RSGATE MGATE RAMP SGATE1 SGATE2 2.5V SLAVE2 VIN 0.1F RTB1 TRACK1 RTA1 RTB2 TRACK2 FB2 VIN FAULT ON GND PGTMR STATUS/PGI
2926 F08
W
U
U
D1 D2 VCC RAMPBUF S1 S2 RFB1 LTC2926 FB1 RFA1 RFB2 RFA2
10k STATUS
CPGTMR
Figure 8. Typical Application Without Master Supply
current pulls the FAULT pin voltage high. When an upstream monitor signal pulls FAULT below 0.5V, the LTC2926's internal fault latch is set, which immediately opens the remote sense switches and cuts off the master and slave supplies by pulling MGATE, SGATE1 and SGATE2 to GND. A fault also activates the internal MOSFET pull-down on the STATUS/PGI pin, which indicates to external downstream monitoring circuits that the supplies are no longer valid (see Status Output). Until the fault latch is reset, the supplies stay disconnected and an internal pull-down keeps the FAULT pin low as a signal to upstream monitors. Fault latch reset is initiated by bringing the ON pin voltage below 0.5V, and completed when PGTMR is <0.1V. Reducing the VCC pin voltage below VCC(UVLO) - VCC(UVLO), typically 2.35V, also resets the fault latch. After it is cleared, the fault latch is armed by bringing the ON pin voltage above 0.6V. No faults can be latched until after the latch is armed. The FAULT pin is pulled up by 8.5A to VCC through a Schottky diode, which allows the pin to be pulled safely above the LTC2926's supply if required. Leave the FAULT pin unconnected if it is unused.
2926fa
13
LTC2926 APPLICATIO S I FOR ATIO
Status Output The output aspect of the STATUS/PGI pin allows the LTC2926 to control and communicate with external downstream circuits. The pin is driven internally by an N-channel MOSFET pull-down to GND and a 10A pullup to an internal charge pump. The pull-down keeps the STATUS/PGI pin low until MGATE, SGATE1 and SGATE2 are fully enhanced, and the remote sense switches are closed. The pull-down then shuts off, and STATUS/PGI pin rises, indicating to downstream monitors that the supplies are fully ramped up. The STATUS/PGI pin pulls low when the MGATE, SGATE1, SGATE2 or RSGATE pin is low, either because a fault has been latched, or because the ON pin is low. An internal charge pump rail at VCC + 5.5V sources the STATUS/PGI pull-up current. An external resistor may be added to create logic level voltages, or the pin may be used to enhance the gates of external N-channel MOSFET switches, if desired. Power Good Timeout The input aspect of the STATUS/PGI pin allows external downstream monitoring circuits to control the LTC2926 as shown in Figure 9. The power good timeout circuit disconnects the supply generators if for any reason the voltage level of the STATUS/PGI pin is not high after the timeout period. During a ramp-up, the timeout circuit will trip if the internal pull-down on STATUS/PGI fails to release, which indicates that supply ramping was not completed in the
1.8V SOURCE Q1 1.8V SLAVE1 10 2.5V SOURCE
Q2 LTC2904 10 V2 RST RFB1 RFA1 V1 S2 S1 TOL
SGATE1 SGATE2 ON/OFF ON LTC2926 STATUS/PGI GND PGTMR FB2
2926 F09
RST GND
FB1
LOAD VOLTAGE MONITOR (10% TOLERANCE)
RFB2 RFA2
CPGTMR
Figure 9. External Load Monitor Controlling LTC2926 via Power Good Input
14
U
time allotted. If supply ramping completes, any downstream circuits that pull down the STATUS/PGI pin after the timer duration also will trip the timeout circuit. A fault caused by a power good timeout has the same effect as a fault triggered by the FAULT pin: supplies are disconnected and the fault latch is set. The fault latch may be cleared as described in the Fault Input/Output section above. The power good timer duration is configured by a capacitor tied between PGTMR and GND. The pin's 10A current source ramps up the capacitor voltage when the ON pin is high, otherwise 4mA pulls PGTMR to GND. The capacitor, CPGTMR, required to configure the power good timeout duration, tPGTMR, is determined from: CPGTMR = 10A * tPGTMR 1.23V If the power good timeout feature is not used, tie PGTMR to GND. Retry on Fault The LTC2926 continuously attempts to ramp up the supplies after a fault if the FAULT pin is tied to the ON pin. When the FAULT and ON pins go low together, the internal fault latch is set by the falling FAULT pin, and the fault latch is reset by the falling ON pin. A short internal delay of several microseconds guarantees triggering of fast pull-down circuits on the RSGATE, MGATE, SGATE1 and SGATE2 pins, which opens the remote sense switches and disconnects the master and slave supplies before the fault latch is reset. If no external signal pulls down the FAULT pin, the internal 8.5A pull-up current or an external pull-up resistor increases the ON (and FAULT) pin voltage above 0.6V, which arms the fault latch. A ramp-up begins when ON is above 1.23V. In applications where the LTC2926 is configured for fault retry, some details of the retry behavior are determined by the source and duration of the fault signal. When a fault is triggered by an external pull-down signal on the FAULT (and ON) pin, supply ramping will not restart until the low input ceases. When a power good fault is triggered by an external pull-down signal on the STATUS/PGI pin, supply ramping restarts immediately. If the low signal persists
2926fa
2.5V SLAVE2
W
U
U
LTC2926 APPLICATIO S I FOR ATIO
through the power good timeout period, a fault and retry will subsequently occur. To ensure a consistent power good timeout period, the LTC2926 requires the PGTMR pin voltage to fall below 0.1V for the fault latch reset to complete. The ON pin needs to be held low for only 10s to initiate fault reset; it is allowed to go high while the timing capacitor on PGTMR discharges to 0.1V (see Functional Block Diagram). When a resistive voltage divider drives the ON and FAULT pins together, include the contribution of IFAULT(UP) when choosing the resistor values (Figure 10a). When a logic output drives both pins, up to 30k of series resistance may be added to limit the output current while the fault pull-down is active (Figure 10b).
VIN VCC ON VCC IFAULT(UP) LTC2926
RONB
VON
RONA
FAULT RONA VON = *V RONA + RONB IN + (RONA || RONB) * IFAULT(UP) GND
FAULT LATCH Q S R
(a)
VIN
RSERIES IOUT
VCC ON VCC IFAULT(UP)
LTC2926
FAULT LIMIT IOUT WITH RSERIES RSERIES 30k
FAULT LATCH Q GND S R
2926 F10
(b)
Figure 10. Fault Retry Configurations, (a) Resistive Voltage Divider and (b) Logic Driven
2926fa
U
Automatic Remote Sense Switching The LTC2926 provides integrated remote sense switches that solve the problem of voltage drops in the external series MOSFETs that control supply ramping. A switch creates a feedback path from a slave supply output to the slave supply generator sense input that allows the generator to compensate for the I * R drop across the controlling MOSFET (see, for example, Figure 6). After the supply ramping is complete, but before the internal pull-down releases the STATUS/PGI pin, the two integrated remote sense switches are closed. For applications that require more than two remote sense switches, connect the RSGATE pin to the gates of additional external N-channel MOSFETs. An internal charge pump guarantees that RSGATE will reach VCC + 5.5V, which allows full enhancement of logic-level MOSFETs with source or drain voltages up to VCC. The switches are open when supply ramping has not completed to avoid creating a power path between the supply generator and the load. When the remote sense switches are open, the supply generator's sense input must be connected locally to its output through a resistor that is much larger than the remote sense switch resistance of 10 (max); a 100 resistor is adequate for most applications as in Figure 7. Some supply modules have built-in resistors of 10 or less between their out and sense pins, which may require a lower switch resistance. Choose an external N-channel MOSFET with an RDS(on) that is at most 1/10 the module out-to-sense resistance, but that is still much larger than the RDS(on) of the power path MOSFET. If neither external remote sense switches nor a status activation delay is required, leave the RSGATE pin unconnected.
W
U
U
15
LTC2926 APPLICATIO S I FOR ATIO
SUPPLY MODULE OUT RX ISW SENSE MGATE Q3 + VDS - Q0 MASTER SUPPLY LOAD
RSGATE
(a)
+ VDS - VOUT RX ISW VSENSE RSW RDS VSUPPLY IL
(b)
2926 F11
Figure 11. Supply and Sense Path Detail, (a) Functional Diagram and (b) Equivalent Circuit When Remote Sense Switch Is Closed
Considerations when Using Remote Sense Switches Consider the supply and sense path detail functional diagram and equivalent circuit in Figure 11. For proper compensation of the I * R drop across the external control MOSFET Q0 by the supply module, the voltage at its sense pin input must be equal to the supply voltage at the load. Solving for VSENSE in the equivalent circuit yields: RX RSW VSENSE = * VSUPPLY + * VOUT R X + RSW R X + RSW For the best compensation, i.e., VSENSE VSUPPLY, choose RX >> RSW. The remote sense switch is intended to be a low-current voltage feedback path. The control MOSFET (Q0 in Figure 11a) should carry all but a tiny fraction of the entire load current. The remote sense switch current is: RDS ISW = ILOAD * R X + RSW + RDS
16
U
To minimize switch current, choose RX >> RDS. In applications that use the LTC2926's integrated remote sense switches, ISW must not exceed the Absolute Maximum Ratings for switch pin currents. It is recommended design practice to satisfy both resistance value conditions. SGATE Voltage at Ramp Start/End When the master ramp is 0V (before ramp up or after ramp down), the control MOSFET ideally conducts no current. If the tracking profile has no delay or offset, the gate control loops may force the SGATE pins either to ground or to just below the MOSFET threshold voltage, depending on reference offsets, resistor mismatches and the load resistance. In both cases the slave load will be at about 0V, but if a known state of SGATE is desired, include an offset in the tracking profile. To guarantee grounding of the SGATE pins at RAMP = 0V, include a positive offset, VOS, based on the maximum slave supply voltage, VSLAVE(max), and the tracking/feedback resistor tolerance. Note that at the start of ramp up, the gate capacitance of the MOSFET must be charged to the threshold voltage before the source begins ramping. The SGATE pins do provide extra current to speed the initial charging. Calculate the required VOS from: VOS k * VSLAVE(max) For 1% resistors k = 1/8, for 5% resistors k = 1/4, for 10% resistors k = 2/5. To guarantee the SGATE pins sit at the MOSFET threshold voltages at RAMP = 0V, include a negative offset. Note that when the master ramp goes to 0V, the slave supplies will remain above ground by the magnitude of the offset. Calculate the required VOS from: VOS -k * VSLAVE(max)
2926fa
W
U
U
LTC2926 APPLICATIO S I FOR ATIO
Q0 SUPPLY MODULE VIN IN OUT RX1 SENSE 10 10 VIN Q1 MASTER SLAVE1
SUPPLY MODULE Q2 VIN IN OUT RX2 SENSE VCC D1 D2 RAMPBUF RTB1 TRACK1 RTA1 RTB2 TRACK2 RTA2 10k FAULT ON/OFF FAULT ON GND PGTMR STATUS/PGI
2926 F12
0.1F
CMGATE 10 MGATE RAMP SGATE1 SGATE2
S1 S2 RFB1 FB1 LTC2926 RFA1 RFB2
VIN
FB2 VIN 10k STATUS RFA2
CPGTMR
Figure 12. Three-Supply Application
Three-Step Design Procedure The following three-step design procedure allows one to choose the FBn resistors, RFAn and RFBn, the TRACKn resistors, RTAn and RTBn, and the master ramp capacitor, CMGATE, that give any of the tracking or sequencing profiles shown in Figures 1 to 4. A three-supply application circuit is shown in Figure 12. 1. Set the ramp rate of the master signal. Solve for the value of CMGATE, the capacitor on the MGATE pin, based on the desired ramp rate (volts per second) of the master ramp signal, SM, and the MGATE pull-up current IMGATE, which is nominally 10A. CMGATE = IMGATE SM (1)
If the master ramp signal is a master supply, consider the gate capacitance of the required external N-channel MOSFET. If the gate capacitance is comparable to CMGATE, reduce the external capacitor's value to compensate for the gate capacitance of the MOSFET.
U
If the master ramp signal is not a master supply, tie the RAMP pin to the MGATE pin. 2. Choose the feedback resistors based on the slave supply voltage and slave load.
SLAVE2
W
U
U
It is important that the feedback resistors are significantly larger than the load resistance, especially as the slave voltage nears ground (see Load Requirements). First determine the effective slave load resistance, RL (not shown), at low slave voltage levels, and select the value of the top feedback resistor, RFB, to satisfy: RFB 100 * RL (recommended), RFB 23 * RL (required) (2)
Second, determine a value for the lower feedback resistor, RFA, that will ensure that the LTC2926 fully enhances the gate of the slave control MOSFET at the end of ramping. Select RFA based on RFB, the resistor tolerance, TOLR, and the maximum slave supply voltage, VSLAVE(max): 1- TOLR RFA < RFB * 1+ TOLR VSLAVE (max) 0.784V - 1 (3)
Note: Choose the value of VSLAVE(max) to cover all slave supply voltage tolerances by a good margin. Exceeding the VSLAVE(max) voltage used for this calculation can result in triggering a Power Good Fault unintentionally. If the slave generator has an accessible resistive divider and a ground-based voltage reference, it may be able to be controlled without a series MOSFET. In that case, let the generator's design set RFA and RFB, substitute the generator's reference voltage for VFB(REF) in step 3, and see the subsection Slave Control Without MOSFETs. 3. Solve for the tracking resistors that set the desired ramp rate and voltage offset or time delay of the slave supply. Choose a ramp rate for the slave supply, SS. If the slave supply tracks coincidently with the master supply or with only a fixed offset or delay, then the slave ramp rate equals the master ramp rate. Be sure that the slave ramp rate and its offset or delay allows the slave voltage to finish ramping
2926fa
17
LTC2926 APPLICATIO S I FOR ATIO U
MASTER SLAVE2 SLAVE1 500mV/DIV 500mV/DIV 5ms/DIV
2926 F13
Figure 13. Coincident Tracking Waveforms from Figure 14 Circuit
before the master ramp reaches its final value; otherwise, the slave supply voltage will be held below its intended level. Calculate the upper track resistor, RTB, from: S R TB = RFB * M SS (4)
Choose a voltage difference between the master and slave ramps, V, if offset tracking is desired. If a time delay is desired for supply sequencing, calculate an effective voltage difference based on the master ramp rate. If neither voltage offset nor time delay is required, set V = 0V. V = a voltage difference (offset tracking), or V = SM * tDLY (supply sequencing), or V = 0V (coincident/ratiometric tracking) (5a) (5b) (5c)
Use the following formula to determine the lower track resistors, RTA, using the TRACK pin voltage, VTRACK, and the FB pin internal reference voltage, VFB(REF), both from the Electrical Characteristics: R TA = VTRACK VFB(REF ) RFB + VFB(REF ) RFA V V - TRACK + R TB R TB (6)
Note that large ratios of slave ramp rate to master ramp rate, SS/SM, may result in negative values for RTA. In such cases increase the offset or delay, or reduce the slave ramp rate to realize positive values of RTA.
18
W
U
U
5ms/DIV
Coincident Tracking Example A typical three-supply application is shown in Figure 14. The master signal is 3.3V, the slave 1 supply is a 1.8V module, and the slave 2 supply is a 2.5V module. Allow for 10% tolerance of the slave supply voltages. Both slave supplies track coincidently with the 3.3V master supply that is controlled by an external MOSFET. The ramp rate of the supplies is 100V/s. The slave supplies' minimum load resistances are 150. The external configuration resistors
Q0 IRF7413Z 1.8V MODULE 3.3V IN OUT RX1 100 SENSE 10 10 3.3V VIN Q1 IRF7413Z 3.3V MASTER 1.8V SLAVE1
2.5V MODULE 3.3V IN OUT RX2 100 SENSE 0.1F CMGATE 0.1F
Q2 IRF7413Z
2.5V SLAVE2
10 VCC D1 D2 RAMPBUF RTB1 15.0k TRACK1 FB1 LTC2926 TRACK2 RFA1 9.53k FB2 RFB2 15.0k RFA2 5.76k STATUS NC RTA1 9.53k S1 S2 RFB1 15.0k MGATE RAMP SGATE1 SGATE2
RTB2 15.0k RTA2 5.76k
VIN 10k
VIN 10k
FAULT ON/OFF
FAULT ON GND PGTMR
STATUS/PGI RSGATE
2926 F14
CPGTMR 1F
Figure 14. Coincident Tracking Example
2926fa
LTC2926 APPLICATIO S I FOR ATIO
have 1% tolerance. The 3-step design procedure detailed above can be used to determine component values. Only the slave 1 supply is considered here, as the procedure is the same for the slave 2 supply. 1. Set the ramp rate of the master signal. From Equation 1: CMGATE = 10A = 0.1F 100 V s
2. Choose the feedback resistors based on the slave supply voltage and slave load. RL = 150 From Equation 2: RFB 100 * 150 = 15k Choose RFB = 15.0k. From Equation 3: 0.99 RFA < 15.0k * 1.01 Choose RFA = 9.53k. 3. Solve for the tracking resistors that set the desired ramp rate and voltage offset or time delay of the slave supply. From Equation 4: 100 V s R TB = 15.0k * = 15.0k 100 V s 1.98 V 0.784V - 1 = 9.64k
U
Since no offset or delay is required, Equation 5c applies: V = 0V From Equation 6: R TA = 0.8 V = 9.53k 0.8 V 0.8 V 0.8 V 0V + - + 15.0k 9.53k 15.0k 15.0k In this example, all supplies remain low while the ON pin is held below 1.23V. When the ON pin rises above 1.23V, 10A pulls up CMGATE and the gate of MOSFET Q0 at 100V/s. The source of Q0 follows the gate and pulls up the output to 3.3V at the rate of 100V/s. This output serves as the master ramp and is buffered from the RAMP pin to the RAMPBUF pin. As the master output and the RAMPBUF pin rise, the current from the TRACK pins is reduced. Consequently, the voltage at the FB pins begins to fall below 0.8V, which causes the SGATE pins to rise. The sources of the slave supply MOSFETs, Q1 and Q2, follow the rising SGATE signals, and the slave supplies track the master supply. When all the supplies have finished ramping, the RSGATE pin voltage rises to close the integrated remote sense switches, which allows the slave supply modules to compensate for voltage drops in the series MOSFETs. If the supplies have ramped within the power good timeout period (about 123ms in this example), the STATUS/PGI pin will rise, indicating completed ramping. When the ON pin is again pulled below 1.23V, the STATUS/PGI pin falls and the RSGATE pin falls, which opens the remote sense switches. Next, 10A will pull down CMGATE and the gate of MOSFET Q0 at 100V/s. If the loads on the outputs are sufficient, all outputs will track down coincidently at 100V/s.
2926fa
W
U
U
19
LTC2926 APPLICATIO S I FOR ATIO U
SLAVE2 SLAVE1 500mV/DIV 500mV/DIV 5ms/DIV
2926 F15
Figure 15. Ratiometric Tracking Waveforms from Figure 16 Circuit
Ratiometric Tracking Example This example converts the coincident tracking example to the ratiometric tracking profile shown in Figure 15, using two slave supplies and a master ramp signal (not a master ramp supply). The ramp rate of the master signal remains unchanged (Step 1), the minimum load resistance of the slave loads remains unchanged (Step 2), and there is no delay in ratiometric tracking. Only Step 3 of the three-step design procedure needs to be considered. In this example,
1.8V MODULE 3.3V IN OUT RX1 100 SENSE 10 Q1 IRF7413Z 1.8V SLAVE1
2.5V MODULE 3.3V IN OUT RX2 100 SENSE 3.3V VIN 0.1F CMGATE 0.1F
VCC D1 D2 RAMPBUF RTB1 24.9k TRACK1 RTB2 18.2k RTA2 5.36k 10k FAULT ON/OFF FAULT ON RTA1 7.68k TRACK2 VIN
MGATE RAMP SGATE1 SGATE2
LTC2926
GND
PGTMR CPGTMR 1F
Figure 16. Ratiometric Tracking Example
20
W
U
U
5ms/DIV
the ramp rate of the 1.8V slave supply is 60V/s, and the ramp rate of the 2.5V supply is 83.3V/s. Always verify that the chosen ramp rate will allow the supplies to ramp-up completely before RAMPBUF reaches VCC. If the 1.8V slave supply were to ramp up at 50V/s it would only reach 1.65V because the RAMPBUF signal would reach its final value of VCC = 3.3V before the slave supply reached 1.8V. 3. Solve for the tracking resistors that set the desired ramp rate and voltage offset or time delay of the slave supply. From Equation 4: 100 V s R TB = 15.0k * = 25k 60 V s Choose RTB = 24.9k. Since no offset or delay is required, Equation 5c applies: V = 0V From Equation 6:
Q2 IRF7413Z
2.5V SLAVE2
10
S1 S2 RFB1 15.0k FB1 RFA1 9.53k FB2 RFB2 15.0k RFA2 5.76k STATUS NC
R TA =
0.8 V 0.8 V 0.8 V 0.8 V 0V + - + 15.0k 9.53k 24.9k 24.9k
= 7.61k
VIN 10k
Choose RTA = 7.68k.
STATUS/PGI RSGATE
2926 F16
2926fa
LTC2926 APPLICATIO S I FOR ATIO U
MASTER SLAVE2 SLAVE1 500mV/DIV 500mV/DIV 5ms/DIV
2926 F17
Figure 17. Offset Tracking Waveforms from Figure 18 Circuit
Offset Tracking Example Converting the circuit in the coincident tracking example to the offset tracking profile shown in Figure 17 is relatively simple. Here the 1.8V slave supply ramps up 1V below the master, and the 2.5V slave supply ramps up 0.5V below the master. The ramp rate remains the same (100V/s), as do the slave supplies' minimum load resistances, so there are no changes necessary to steps 1 or 2 of the three-step
Q0 IRF7413Z 1.8V MODULE 3.3V IN OUT RX1 100 SENSE 10 10 3.3V VIN Q1 IRF7413Z 3.3V MASTER 1.8V SLAVE1
2.5V MODULE 3.3V IN OUT RX2 100 SENSE 0.1F CMGATE 0.1F
VCC D1 D2 RAMPBUF RTB1 15.0k TRACK1 RTB2 15.0k RTA2 4.64k 10k FAULT ON/OFF FAULT ON RTA1 5.36k TRACK2 VIN
MGATE RAMP SGATE1 SGATE2
LTC2926
GND
PGTMR CPGTMR 1F
Figure 18. Offset Tracking Example
W
U
U
5ms/DIV
design procedure. Only step 3 must be considered. Be sure to verify that the chosen voltage offsets will allow the slave supplies to ramp up completely. In this example, if the voltage offset on the 1.8V supply were 2V, it could ramp up only to 3.3V - 2V = 1.3V. 3. Solve for the tracking resistors that set the desired ramp rate and voltage offset or time delay of the slave supply. From Equation 4: 100 V s R TB = 15.0k * = 15k 100 V s Choose RTB = 15.0k.
Q2 IRF7413Z
Since offset is required, Equation 5a applies:
2.5V SLAVE2
V = 1.0V From Equation 6: R TA = 0.8 V 0.8 V 0.8 V 0.8 V 1.0 V + - + 15.0k 9.53k 15.0k 15.0k = 5.31k
10
S1 S2 RFB1 15.0k FB1 RFA1 9.53k FB2 RFB2 15.0k RFA2 5.76k STATUS NC
Choose RTA = 5.36k.
VIN 10k
STATUS/PGI RSGATE
2926 F18
2926fa
21
LTC2926 APPLICATIO S I FOR ATIO U
SLAVE2 SLAVE1 500mV/DIV 500mV/DIV 5ms/DIV
2926 F19
Figure 19. Supply Sequencing Waveforms from Figure 20 Circuit
Supply Sequencing Example In Figure 19, the two slave supplies are sequenced using a master ramp signal. As in the ratiometric tracking example, the master signal ramps up at 100V/s, and the minimum slave loads are the same as the coincident example, so steps 1 and 2 remain the same. The 1.8V slave 1 supply ramps up at 1000V/s beginning 10ms after the master signal starts to ramp up. The 2.5V slave 2 supply ramps up at 1000V/s beginning 20ms after the master signal
1.8V MODULE 3.3V IN OUT RX1 100 SENSE 10 Q1 IRF7413Z 1.8V SLAVE1
2.5V MODULE 3.3V IN OUT RX2 100 SENSE 3.3V VIN 0.1F CMGATE 0.1F
VCC D1 D2 RAMPBUF RTB1 1.50k TRACK1 RTB2 2.49k RTA2 1.33k 10k FAULT ON/OFF FAULT ON RTA1 2.94k TRACK2 VIN
MGATE RAMP SGATE1 SGATE2
LTC2926
GND
PGTMR CPGTMR 1F
Figure 20. Supply Sequencing Example
22
W
U
U
5ms/DIV
starts to ramp up. Note that not every combination of ramp rates and delays is possible. Small delays and large ratios of slave ramp rate to master ramp rate may result in solutions that require negative resistors. In such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced. 3. Solve for the tracking resistors that set the desired ramp rate and voltage offset or time delay of the slave supply. From Equation 4: 100 V s R TB = 15.0k * = 1.5k 1000 V s Choose RTB = 1.50k.
Q2 IRF7413Z
2.5V SLAVE2
Since a delay is required, Equation 5b applies: V = 100V/s * 10ms = 1V From Equation 6: R TA = 0.8 V = 2.96k 0.8 V 0.8 V 0.8 V 1V + - + 15.0k 9.53k 1.50k 1.50k
10
S1 S2 RFB1 15.0k FB1 RFA1 9.53k FB2 RFB2 24.9k RFA2 9.53k STATUS NC
Choose RTA = 2.94k. Note that the values of RFA2 and RFB2 are larger than those of the Coincident Tracking Example. Larger feedback resistor values resulted in larger tracking resistor values for RTA2 and RTB2, which limits the maximum TRACK2 pin current to <1mA; see Final Sanity Checks.
VIN 10k
STATUS/PGI RSGATE
2926 F20
2926fa
LTC2926 APPLICATIO S I FOR ATIO
Slave Control Without MOSFETs The LTC2926 can control tracking and sequencing of a slave supply without a MOSFET if the supply generator's output voltage is set by an accessible resistive voltage divider and if its voltage reference is ground-based. Tracking currents mirrored to the FB pins are injected into the feedback nodes of the supply generators to control the output voltage. When master ramp signal has reached it maximum voltage, the FB pin current is zero, and the LTC2926 has no effect on the output voltage accuracy, transient response or stability of the generator. To control a supply generator (e.g., DC/DC converter) with a feedback reference voltage VFB(GEN) of 0.75V or less, connect the FB pin of the LTC2926 to the tap point of the generator's resistive divider, as shown in Figure 21a. Follow steps 1 and 3 of the Three-Step Design Procedure to set the ramp rates and tracking profile. Use the feedback resistor values required by the supply generator for RFA and RFB in step 3. A generator with VFB(GEN)>0.75V may be controlled without a MOSFET if the slave voltage is large enough (see Figure 22). First follow steps 1 and 3 of the Three-Step Design Procedure to set the ramp rates and tracking profile.
SUPPLY GENERATOR VIN IN OUT SLAVE VIN IN
SUPPLY GENERATOR OUT SLAVE 6 RFB + VFB(GEN) RFA RFAB RFAA VSLAVE (V) FB GND FB - 5 4 3 2 1 0 0
RFB + VFB(GEN) GND -
LTC2926 RAMPBUF SGATE RTB TRACK RTA FB GND RTA NC RTB
LTC2926 RAMPBUF SGATE FB GND
2926 F21
TRACK
(a)
Figure 21. Slave Supply Control Without a MOSFET (a) Generator Reference VFB(GEN) 0.75V and (b) Generator Reference VFB(GEN) > 0.75V
U
Use the feedback resistor values required by the supply generator in step 3. Next, split resistor RFA as in Figure 21b, so that RFAA RFA * 0.75V and VFB(GEN) RFAB = RFA - RFAA and tie the LTC2926's FB pin to the node in between. The new tap point allows the LTC2926's FB pin to see <0.75V at the end of ramp-up. Finally, scale the track resistors to match RFAA: R = TA R = TB RFAA * R and RFAA + RFAB TA RFAA *R RFAA + RFAB TB Voltage regulators that force their reference voltage between their output and feedback nodes do not employ a ground-based reference, and thus will not be controllable by the LTC2926 without a series MOSFET.
Slave Supply Control Without a MOSFET
CONTROL VIA FB PIN AND SPLIT RFA RESISTOR CONTROL VIA FB PIN NC MOSFET CONTROL ONLY 0.25 0.50 0.75 1.00 VFB(GEN) (V) 1.25 1.50
W
U
U
(b)
2926 F22
Figure 22. Regions of Possible Slave Control Without a MOSFET
2926fa
23
LTC2926 APPLICATIO S I FOR ATIO
Final Sanity Checks The collection of equations below is useful for identifying unrealizable solutions. As stated in step 3 of the design procedure, the slave supply must finish ramping before the master signal has reached its final voltage. This can be verified with the following equation: R VMASTER > VTRACK * 1+ TB R
TA
Here, VTRACK = 0.8V. VMASTER is the final voltage of the master signal, either the supply voltage ramped up through the optional external MOSFET or VCC when no MOSFET is present. It is possible to choose resistor values that require the LTC2926 to supply more current than the Electrical Characteristics table guarantees. To avoid this condition, check that each TRACK pin's current, ITRACKn, does not exceed 1mA, and that the RAMPBUF pin current, IRAMPBUF, does not exceed 3mA. To confirm that ITRACKn 1mA, verify that: VTRACK 1mA R TA || R TB Check that the RAMPBUF pin will not be forced to sink more than 3mA when it is at 0V and will not be forced to source more than 3mA when it is at VMASTER. VTRACK VTRACK + 3mA and R TA1 || R TB1 R TA 2 || R TB2 VMASTER V + MASTER 3mA R TA1 + R TB1 R TA 2 + R TB2
24
U
Load Requirements A weak resistive load can cause static and dynamic tracking errors. The behavior of the source-follower topology of MOSFET-controlled tracking relies on the load's ability to support the ramp rates and tracking currents of a particular application. Consider the simplified slave load schematic in Figure 23.
SUPPLY MODULE Qn OUT RFB SGATEn FBn LTC2926 RL CL SLAVEn LOAD RFA
2926 F23
W
U
U
Figure 23. Simplified Slave Supply Load
When the supplies are ramped down quickly, the load must be capable of sinking enough current to support the ramp rate. For example, if there is a large output capacitance and a weak resistive load on a particular supply, that supply's falling rate will be limited by the RC time constant of the load. In Figure 24, the falling 2.5V slave cannot keep up with the falling master ramp. When the supplies are near ground, the load must be capable of sinking the tracking current without creating a large offset voltage. For weak resistive loads and slave voltage levels near ground, the tracking current (at its maximum there) can be in excess of the load's current demand. Having no capability for sinking current, the MOSFET shuts off. All of the mirrored tracking current that flows through RFB also flows through the load resistance, RL, which creates a voltage offset between the slave and ground. In Figure 24, the 1.8V supply shows an offset from ground.
2926fa
LTC2926 APPLICATIO S I FOR ATIO
MASTER SLAVE2 SLAVE1 LARGE L = RLCL RL RFB 500mV/DIV
5ms/DIV
2926 F24
Figure 24. Tracking Effects of Weak Resistive Load
Under worst-case conditions, FB pin voltages may reach the maximum clamp voltage of 2.4V. To limit the slave voltage offset to below 100mV, choose RFB 23 * RL. Add a resistor in parallel with the load to strengthen weak resistive loads as required. Start-Up Delays Often power supplies do not start up immediately when their input supplies are applied. If the LTC2926 tries to ramp up these power supplies as soon as the input supply is present, the start-up of the outputs may be delayed, which defeats the tracking circuit. Make sure the ON pin does not initiate ramp-up until all supply sources are available. RAMP Pin Clamp
The RAMP pin is weakly clamped to the VCC pin. When MGATE and RAMP are tied together their pin voltages will not exceed VCC + 1V. If the RAMP pin is driven by a low impedance source that can exceed VCC, include a series resistor to limit the current to <20A. Use 50k per source volt above VCC.
U
Layout Considerations Be sure to place a 0.1F bypass capacitor as near as possible to the supply pin of the LTC2926. To minimize the noise on the slave supplies' outputs, keep the traces connecting the FB pins of the LTC2926 and the feedback nodes of the slave supplies' resistive voltage dividers as short as possible. In addition, do not route those traces next to signals with fast transitions times. To get the best compensation of the series I * R drops of the external MOSFETs, make sure the supply output nodes and the supply generator sense connections use Kelvin-sensing. The feedback resistive voltage divider should Kelvin-sense the slave supply output node for accuracy, as well.
SUPPLY MODULE Q1 OUT 100 SENSE GND KELVIN-SENSE CONNECTIONS 10 D1 SGATE1 S1 KELVIN-SENSE CONNECTIONS MINIMIZE TRACE LENGTH VCC 0.1F GND LTC2926 FB1 RFB MINIMIZE TRACE LENGTH RFA SLAVE LOAD KELVIN-SENSE CONNECTIONS
2926 F25
W
U
U
Figure 25. Layout Considerations
2926fa
25
LTC2926 PACKAGE DESCRIPTIO U
GN Package 20-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 - .344* (8.560 - 8.738) 20 19 18 17 16 15 14 13 12 11 .045 .005 .058 (1.473) REF .150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) .0250 BSC 1 .0532 - .0688 (1.35 - 1.75) 23 4 56 7 8 9 10 .004 - .0098 (0.102 - 0.249) .015 .004 x 45 (0.38 0.10)
.0075 - .0098 (0.19 - 0.25) 0 - 8 TYP
.254 MIN
.0165 .0015 RECOMMENDED SOLDER PAD LAYOUT
.016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS)
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN20 (SSOP) 0204
2926fa
26
LTC2926 PACKAGE DESCRIPTIO U
UFD Package 20-Lead Plastic QFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1711)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.65 0.05 (2 SIDES) 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 0.10 (2 SIDES) 0.75 0.05 2.65 0.10 (2 SIDES) R = 0.115 TYP 19 20 PIN 1 NOTCH R = 0.30 TYP 0.40 0.05 1 2 5.00 0.10 (2 SIDES) 3.65 0.10 (2 SIDES)
(UFD20) QFN 0304
4.50 0.05 2.65 0.05 3.10 0.05 (2 SIDES)
PIN 1 TOP MARK (NOTE 6)
0.200 REF 0.00 - 0.05
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
2926fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2926 TYPICAL APPLICATIO U
Chaining to Track/Sequence More Supplies
SUPPLY GENERATOR 4 Q4 VIN IN OUT RX4 SENSE SUPPLY GENERATOR 3 Q3 VIN IN OUT RX3 SENSE VCC 0.1F ON MGATE RAMP RAMPBUF D1 D2 10 SGATE1 SGATE2 S1 S2 RFB3 FB1 LTC2926 RFA3 RFB4 FB2 TRACK1 RTA3 RTB4 TRACK2 RTA4 SUPPLY GENERATOR 2 Q2 VIN IN OUT RX2 SENSE SUPPLY GENERATOR 1 Q1 VIN IN OUT RX1 SENSE D1 VCC RONB 0.1F ON RONA MGATE CMGATE RTB1 TRACK1 RTA1 RTB2 TRACK2 RTA2 RSGATE FAULT GND PGTMR STATUS/PGI CPGTMR
2926 TA02
SLAVE4
10 SLAVE3
NC
VCC
RTB3
RSGATE FAULT GND PGTMR STATUS/PGI
NC
RFA4
10k
10k
SLAVE2
10 SLAVE1
10 D2 SGATE1 SGATE2 S1 S2 RFB1 FB1 RFA1 RAMP RAMPBUF LTC2926 FB2 RFA2 RFB2
NC FAULT STATUS
RELATED PARTS
PART NUMBER LTC2908 LTC2920-1/LTC2920-2 LTC2921/LTC2922 LTC2923 LTC2925 LTC2927 DESCRIPTION Precision Six Supply Monitor Single/Dual Power Supply Margining Controllers Power Supply Trackers with Input Monitors Power Supply Tracking Controller Multiple Power Supply Tracking Controller with Power Good Timeout Single Power Supply Tracking Controller COMMENTS Four Fixed (Various Levels) and Two Adjustable Input Thresholds Single or Dual, Symmetric/Asymmetric High and Low Margining Monitor up to Five Supplies, Includes Remote Sense Switches Controls Two Supplies Without FETs, MSOP-10 and DFN-12 Packages Controls Three Supplies Without FETs, Includes Three Shutdown Control Pins Controls Single Supply Without FETs, Daisy-Chain for Multiple Supplies
2926fa LT 0506 REV A * PRINTED IN USA
28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

▲Up To Search▲

Price & Availability of LTC2926CUFD

	To Download LTC2926CUFD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .